XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 196
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XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
(362 pages)
- Current page: 196 of 362
- Download datasheet (5Mb)
Enhanced Capture Timer (ECT) Module
13.4.20 Timer Test Register
13.4.21 Timer Port Data Register
Data Sheet
196
NOTE:
Read: Anytime
Write: Only in special mode (SMOD = 1)
TCBYP — Main Timer Divider Chain Bypass Bit
Read: Anytime (input return pin level; outputs return data register contents)
Write: Data stored in an internal latch (drives pins only if configured for output)
Since the output compare 7 register (OC7) shares pins with the pulse accumulator
input, the only way for the pulse accumulator to receive an independent input from
OC7 is by setting both OM7 and OL7 to be 0, and also OC7M7 in OC7M register
to be 0. OC7 can still reset the counter if enabled while PT7 is used as an input to
the pulse accumulator.
PORTT can be read anytime. When configured as an input, a read will return the
pin level. When configured as an output, a read will return the latched output data.
Writes do not change pin state when the pin is configured for timer output. The
minimum pulse width for pulse accumulator input should always be greater than
the width of two module clocks due to input synchronizer circuitry. The minimum
pulse width for the input capture should always be greater than the width of two
module clocks due to input synchronizer circuitry.
Address: $00AD
Address: $00AE
Reset:
Reset:
Timer:
Read:
Read:
Write:
Write:
0 = Normal operation
1 = For testing only. The 16-bit free-running timer counter is divided into two
8-bit halves and the prescaler is bypassed. The clock drives both halves
directly. When the high byte of timer counter TCNT ($84) overflows from
$FF to $00, the TOF flag in TFLG2 ($8F) will be set.
1. Available only on MC68HC912B32 devices.
I/0C7
Bit 7
Bit 7
PT7
Enhanced Capture Timer (ECT) Module
0
0
0
Figure 13-42. Timer Port Data Register (PORTT)
Figure 13-41. Timer Test Register (TIMTST)
= Unimplemented
I/OC6
PT6
6
0
0
6
0
I/OC5
PT5
5
0
0
5
0
I/OC4
PT4
4
0
0
4
0
I/OC3
PT3
3
0
0
3
0
M68HC12B Family — Rev. 8.0
I/OC2
PT2
2
0
0
2
0
TCBYP
I/OC1
PT1
1
0
1
0
MOTOROLA
PCBYP
I/OC0
Bit 0
Bit 0
PT0
0
0
(1)
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