XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 127

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

10.7.5 Arm/Reset COP Timer Register
M68HC12B Family — Rev. 8.0
MOTOROLA
Always reads $00.
Writing $55 to this address is the first step of the COP watchdog sequence.
Writing $AA to this address is the second step of the COP watchdog sequence.
Other instructions may be executed between these writes but both must be
completed in the correct order prior to timeout to avoid a watchdog reset. Writing
anything other than $55 or $AA causes a COP reset to occur.
CR2
Address: $0017
0
0
0
0
1
1
1
1
Reset:
Read:
Write:
CR1
0
0
1
1
0
0
1
1
Figure 10-9. Arm/Reset COP Timer Register (COPRST)
Bit 7
Bit 7
0
Clock Generation Module (CGM)
Table 10-4. COP Watchdog Rates (RTBYP = 0)
CR0
0
1
0
1
0
1
0
1
Bit 6
6
0
Divide E By:
OFF
2
2
2
2
2
2
2
Bit 5
13
15
17
19
21
22
23
5
0
Bit 4
4
0
At E = 4.0-MHz
0 to +2.048 ms
131.072 ms
524.288 ms
8.1920 ms
32.768 ms
2.048 ms
Timeout
1.048 s
2.097 s
OFF
Bit 3
3
0
Clock Generation Module (CGM)
Bit 2
2
0
At E = 8.0-MHz
0 to +1.024 ms
262.144 ms
524.288 ms
1.048576 s
Bit 1
16.384 ms
65.536 ms
1.024 ms
4.096 ms
Timeout
1
0
Clock Registers
OFF
Data Sheet
Bit 0
Bit 0
0
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