XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 248

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Communications (BDLC)
15.8.5.5 Summary
Data Sheet
248
Transmission error
Cyclical redundancy check
(CRC) error
Invalid symbol: BDLC transmits,
but receives invalid bits (noise)
Framing error
Bus short to V
Bus short to GND
BDLC receives BREAK symbol
Error Condition
DD
If the bus is shorted to battery, the BDLC waits for the bus to fall to a passive state
before it attempts to transmit a message. As long as the short remains, the BDLC
never attempts to transmit a message onto the J1850 bus.
If the bus is shorted to ground, the BDLC sees an idle bus, begins to transmit the
message, and then detects a transmission error (in BSVR), since the short to
ground does not allow the bus to be driven to the active (dominant) SOF state. The
BDLC aborts that transmission and waits for the next CPU command to transmit.
In any case, if the bus fault is temporary, as soon as the fault is cleared, the BDLC
resumes normal operation. If the bus fault is permanent, it may result in permanent
loss of communication on the J1850 bus. (See
Register.)
BREAK — If a BREAK symbol is received while the BDLC is transmitting or
receiving, an invalid symbol (in BSVR) interrupt is generated. Reading the BSVR
(see
BDLC waits for the bus to idle, then waits for a start-of-frame (SOF) symbol.
The BDLC cannot transmit a BREAK symbol. It can receive a BREAK symbol only
from the J1850 bus.
Table 15-1
15.9.3 BDLC State Vector
Table 15-1. BDLC J1850 Bus Error Summary
For invalid bits or framing symbols on non-byte boundaries, invalid symbol interrupt
is generated. BDLC stops transmission.
CRC error interrupt is generated.
BDLC waits for EOF.
The BDLC aborts transmission immediately. Invalid symbol interrupt is generated.
Invalid symbol interrupt is generated. BDLC waits for end of frame (EOF).
The BDLC does not transmit until the bus is idle. Invalid symbol interrupt is generated.
EOF interrupt also must be seen before another transmission attempt. Depending on
length of the short, LOA flag also may be set.
Thermal overload shuts down physical interface. Fault condition is seen as invalid
symbol flag. EOF interrupt must also be seen before another transmission attempt.
Invalid symbol interrupt is generated. BDLC waits for the next valid SOF.
provides a bus error summary.
Byte Data Link Communications (BDLC)
Register) clears this interrupt condition. The
BDLC Function
15.9.3 BDLC State Vector
M68HC12B Family — Rev. 8.0
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