XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 220

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Serial Interface
14.3.5.4 SPI Status Register
Data Sheet
220
Read: Anytime
Write: Has no meaning or effect
SPIF — SPI Interrupt Request Bit
WCOL — Write Collision Status Flag
MODF — SPI Mode Error Interrupt Status Flag
SPIF is set after the eighth SCK cycle in a data transfer, and it is cleared by
reading the SP0SR register (with SPIF set) followed by an access (read or write)
to the SPI data register.
The MCU write is disabled to avoid writing over the data being transferred. No
interrupt is generated because the error status flag can be read upon
completion of the transfer that was in progress at the time of the error. This bit
is cleared automatically by a read of the SP0SR (with WCOL set) followed by
an access (read or write) to the SP0DR register.
This bit is set automatically by SPI hardware, if the MSTR control bit is set and
the slave select input pin becomes 0. This condition is not permitted in normal
operation. In the case where DDRS bit 7 is set, the PS7 pin is a general-purpose
output pin or SS output pin rather than being dedicated as the SS input for the
SPI system. In this special case, the mode fault function is inhibited and MODF
remains cleared. This flag is cleared automatically by a read of the SP0SR (with
MODF set) followed by a write to the SP0CR1 register.
Address:
Reset:
Read:
Write:
0 = No write collision
1 = Indicates that a serial transfer was in progress when the MCU tried to
write new data into the SP0DR data register
$00D3
SPIF
Bit 7
0
Figure 14-18. SPI Status Register (SP0SR)
= Unimplemented
WCOL
6
0
Serial Interface
5
0
0
MODF
4
0
3
0
0
M68HC12B Family — Rev. 8.0
2
0
0
1
0
0
MOTOROLA
Bit 0
0
0