XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 210

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Serial Interface
14.2.3.4 SCI Status Register 1
Data Sheet
210
ILIE — Idle Line Interrupt Enable Bit
TE — Transmitter Enable Bit
RE — Receiver Enable Bit
RWU — Receiver Wakeup Control Bit
SBK — Send Break Bit
Read: Anytime; used in auto clearing mechanism
Write: Has no meaning or effect
The bits in these registers are set by various conditions in the SCI hardware and
are cleared automatically by special acknowledge sequences. The receive related
flag bits in SC0SR1 (RDRF, IDLE, OR, NF, FE, and PF) are all cleared by a read
of the SC0SR1 register followed by a read of the transmit/receive data register low
byte. However, only those bits which were set when SC0SR1 was read will be
cleared by the subsequent read of the transmit/receive data register low byte. The
Address:
As long as SBK remains set, the transmitter sends 0s. When SBK is changed
to 0, the current frame of all 0s is finished before the TxD line goes to the idle
state. If SBK is toggled on and off, the transmitter sends only 10 (or 11) 0s and
then reverts to mark idle or sending data.
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
0 = Transmitter disabled
1 = SCI transmit logic is enabled and the TXD pin (port S
0 = Receiver disabled
1 = Enables the SCI receive circuitry
0 = Normal SCI receiver
1 = Enables the wakeup function and inhibits further receiver interrupts.
0 = Break generator off
1 = Generate a break code, at least 10 or 11 contiguous 0s.
Reset:
Read:
Write:
bit 1) is dedicated to the transmitter. The TE bit can be used to queue an
idle preamble.
Normally, hardware wakes the receiver by automatically clearing this bit.
$00C4
TDRE
Bit 7
1
Figure 14-7. SCI Status Register 1 (SC0SR1)
= Unimplemented
Serial Interface
TC
6
1
RDRF
5
0
IDLE
4
0
OR
3
0
M68HC12B Family — Rev. 8.0
NF
2
0
FE
1
0
MOTOROLA
Bit 0
PF
0