XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 238

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Communications (BDLC)
15.7.3.1 Logic 0
Data Sheet
238
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
Figure 15-5. J1850 VPW Symbols with Nominal Symbol Times
(F) END OF FRAME
(C) BREAK
All VPW bit lengths stated in the descriptions here are typical values at a 10.4-Kbps
bit rate. EOF, EOD, IFS, and IDLE, however, are not driven J1850 bus states. They
are passive bus periods observed by each node’s CPU.
A logic 0 is defined as:
See
≥ 240 µs
280 µs
•
•
Figure
An active-to-passive transition followed by a passive period 64 µs in length,
or
A passive-to-active transition followed by an active period 128 µs in length
15-5(A).
Byte Data Link Communications (BDLC)
(G) INTER-FRAME
SEPARATION
128 µs
128 µs
20 µs
300 µs
(A) LOGIC 0
(B) LOGIC 1
(D) START OF FRAME
200 µs
OR
OR
IDLE > 300 µs
(H) IDLE
M68HC12B Family — Rev. 8.0
64 µs
64 µs
(E) END OF DATA
200 µs
MOTOROLA