XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 322

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

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18.3.4 BDM Registers
Data Sheet
322
The external host should delay about 32 target E-clock cycles between a firmware
read command and the data portion of these commands. This allows the BDM
firmware to execute the instructions needed to get the requested data into the BDM
shifter register.
The external host should delay about 32 target E-clock cycles after the data portion
of firmware write commands to allow BDM firmware to complete the requested
write operation before a new serial command disturbs the BDM shifter register.
The external host should delay about 64 target E-clock cycles after a TRACE1 or
GO command before starting any new serial command. This delay is needed
because the BDM shifter register is used as a temporary data holding register
during the exit sequence to user code.
BDM logic retains control of the internal buses until a read or write is completed. If
an operation can be completed in a single cycle, it does not intrude on normal
CPU12 operation. However, if an operation requires multiple cycles, CPU12 clocks
are frozen until the operation is complete.
Seven BDM registers are mapped into the standard 64-Kbyte address space when
BDM is active. Mapping is shown in
The content of the instruction register is determined by the type of background
command being executed. The status register indicates BDM operating conditions.
The shift register contains data being received or transmitted via the serial
interface. The address register is temporary storage for BDM commands. The CCR
holding register preserves the content of the CPU12 condition code register while
BDM is active.
The only registers of interest to users are the status register and the CCR holding
register. The other BDM registers are used only by the BDM firmware to execute
commands. The registers are accessed by means of the hardware READ_BD and
WRITE_BD commands, but should not be written during BDM operation (except
the CCRSAV register which could be written to modify the CCR value).
The instruction register is written by the BDM hardware as a result of serial data
shifted in on the BKGD pin. It is readable and writable in special peripheral mode
$FF02–$FF03
$FF04–$FF05
Address
$FF00
$FF01
$FF06
Development Support
BDM instruction register
BDM status register
BDM shift register
BDM address register
BDM CCR holding register
Table 18-4. BDM Registers
Table
Register
18-4.
M68HC12B Family — Rev. 8.0
INSTRUCTION
Mnemonic
ADDRESS
SHIFTER
CCRSAV
STATUS
MOTOROLA