XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 74

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Resets and Interrupts
4.6.3 Computer Operating Properly (COP) Reset
4.6.4 Clock Monitor Reset
4.7 Effects of Reset
4.7.1 Operating Mode and Memory Map
4.7.2 Clock and Watchdog Control Logic
4.7.3 Interrupts
Data Sheet
74
The MCU includes a COP system to help protect against software failures. When
COP is enabled, software must write $55 and $AA (in this order) to the COPRST
register to keep a watchdog timer from timing out. Other instructions may be
executed between these writes. A write of any value other than $55 or $AA or
software failing to execute the sequence properly causes a COP reset to occur.
If clock frequency falls below a predetermined limit when the clock monitor is
enabled, a reset occurs.
When a reset occurs, MCU registers and control bits are changed to known startup
states, as described here.
The states of the BKGD, MODA, and MODB pins during reset determine the
operating mode and default memory mapping. The SMODN, MODA, and MODB
bits in the MODE register reflect the status of the mode-select inputs at the rising
edge of reset. Operating mode and default maps can subsequently be changed
according to strictly defined rules.
Reset enables the COP watchdog with the CR2–CR0 bits set for the shortest
timeout period. The clock monitor is disabled. The RTIF flag is cleared and
automatic hardware interrupts are masked. The rate control bits are cleared and
must be initialized before the return-from-interrupt (RTI) system is used. The DLY
control bit is set to specify an oscillator startup delay upon recovery from stop
mode.
Reset initializes the HPRIO register with the value $F2, causing the IRQ pin to have
the highest I-bit interrupt priority. The IRQ pin is configured for level-sensitive
operation (for wired-OR systems). However, the I and X bits in the CCR are set,
masking IRQ and XIRQ interrupt requests.
Resets and Interrupts
M68HC12B Family — Rev. 8.0
MOTOROLA