XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 188

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Enhanced Capture Timer (ECT) Module
13.4.11 16-Bit Pulse Accumulator A Control Register
Data Sheet
188
Read: Anytime
Write: Anytime
Sixteen-bit pulse accumulator A (PACA) is formed by cascading the 8-bit pulse
accumulators PAC3 and PAC2. When PAEN is set, the PACA is enabled. The
PACA shares the input pin with IC7.
PAEN — Pulse Accumulator A System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
PAEN is independent from TEN. With timer disabled, the pulse accumulator can
still function unless the pulse accumulator is disabled.
For PAMOD bit = 0, event counter mode
For PAMOD bit = 1, gated time accumulation mode
Address: $00A0
Reset:
Figure 13-29. 16-Bit Pulse Accumulator A Control Register (PACTL)
Read:
Write:
0 = 16-bit pulse accumulator A system disabled. Eight-bit PAC3 and PAC2
1 = Pulse accumulator A system enabled. The two 8-bit pulse accumulators,
0 = Event counter mode
1 = Gated time accumulation mode
0 = Falling edges on PT7 pin cause the count to be incremented.
1 = Rising edges on PT7 pin cause the count to be incremented.
0 = PT7 input pin high enables M divided by 64 clock to pulse accumulator
1 = PT7 input pin low enables M divided by 64 clock to pulse accumulator
can be enabled when their related enable bits in ICPACR ($A8) are set.
Pulse accumulator input edge flag (PAIF) function is disabled.
PAC3 and PAC2, are cascaded to form the PACA 16-bit pulse
accumulator. When PACA in enabled, the PACN3 and PACN2 registers’
contents are, respectively, the high and low byte of the PACA. PA3EN
and PA2EN control bits in ICPACR ($A8) have no effect. Pulse
accumulator input edge flag (PAIF) function is enabled.
and the trailing falling edge on PT7 sets the PAIF flag.
and the trailing rising edge on PT7 sets the PAIF flag.
Bit 7
Enhanced Capture Timer (ECT) Module
0
0
PAMOD
= Unimplemented
0
0
1
1
PAEN
6
0
PEDGE
0
1
0
1
PAMOD
5
0
Falling edge
Rising edge
Divide by 64 clock enabled with pin high level
Divide by 64 clock enabled with pin low level
PEDGE
4
0
CLK1
3
0
Pin Action
M68HC12B Family — Rev. 8.0
CLK0
2
0
PAOVI
1
0
MOTOROLA
Bit 0
PAI
0