XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 163

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

12.3.12 Pulse Accumulator Flag Register
12.3.13 16-Bit Pulse Accumulator Count Register
M68HC12B Family — Rev. 8.0
MOTOROLA
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register
clears all the flags in the PAFLG register.
PAOVF — Pulse Accumulator Overflow Flag
PAIF — Pulse Accumulator Input Edge Flag
Read: Anytime
Write: Anytime
Full count register access should take place in one clock cycle. A separate
read/write for high byte and low byte will give a different result than accessing them
as a word.
Address: $00A1
Address: $00A2
Address: $00A3
Set when the 16-bit pulse accumulator overflows from $FFFF to $0000. This bit
is cleared automatically by a write to the PAFLG register with bit 1 set.
Set when the selected edge is detected at the pulse accumulator input pin. In
event mode, the event edge triggers PAIF. In gated time accumulation mode,
the trailing edge of the gate signal at the pulse accumulator input pin triggers
PAIF. This bit is cleared automatically by a write to the PAFLG register with bit
0 set.
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 12-26. 16-Bit Pulse Accumulator Count Register (PACNT)
Figure 12-25. Pulse Accumulator Flag Register (PAFLG)
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
Standard Timer Module (TIM)
Bit 14
Bit 6
6
0
0
6
0
6
0
Bit 13
Bit 5
5
0
0
5
0
5
0
Bit 12
Bit 4
4
0
0
4
0
4
0
Bit 11
Bit 3
3
0
0
3
0
3
0
Standard Timer Module (TIM)
Bit 10
Bit 2
2
0
0
2
0
2
0
PAOVF
Bit 9
Bit 1
1
0
1
0
1
0
Block Diagram
Data Sheet
PAIF
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
0
0
0
163