XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 250

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Communications (BDLC)
15.9.2 BDLC Control Register 2
Data Sheet
250
IE — Interrupt Enable Bit
WCM — Wait Clock Mode Bit
This register controls transmitter operations of the BDLC.
ALOOP — Analog Loopback Mode Bit
This bit determines whether the BDLC generates CPU interrupt requests in run
mode. It does not clear BSVR interrupts when exiting the BDLC stop or BDLC
wait modes. Interrupt requests are maintained until all of the interrupt request
sources are cleared by performing the specified actions upon the BDLC’s
registers (or an MCU reset sets BSVR bits to $00). Interrupts that were pending
at the time that this bit is cleared may be lost.
If the programmer does not want to use the interrupt capability of the BDLC, the
BDLC state vector register (BSVR) can be polled periodically to determine
BDLC states.
This bit determines the operation of the BDLC during CPU wait mode.
This bit determines if the J1850 bus is driven by the analog physical interface’s
final drive stage. The programmer places the transceiver into loopback mode
Address: $00FA
Reset:
Read:
Write:
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
0 = Run BDLC internal clocks during CPU wait mode.
1 = Stop BDLC internal clocks during CPU wait mode.
f
XCLK
1.049 MHz
2.097 MHz
4.194 MHz
8.389 MHz
1.000 MHz
2.000 MHz
4.000 MHz
8.000 MHz
Frequency
ALOOP
Byte Data Link Communications (BDLC)
Bit 7
1
Figure 15-13. BDLC Control Register 2 (BCR2)
DLOOP
6
1
Table 15-2. BDLC Rate Selection
R1
0
0
1
1
0
0
1
1
RX4XE
5
0
NBFS
R0
0
1
0
1
0
1
0
1
4
0
TEOD
Division
3
0
1
2
4
8
1
2
4
8
M68HC12B Family — Rev. 8.0
TSIFR
2
0
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
TMIFR1
f
BDLC
1
0
MOTOROLA
TMIFR0
Bit 0
0