XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 110

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

FLASH EEPROM
8.4.2 Normal Operation
8.4.3 Program/Erase Operation
8.4.3.1 Read/Write Accesses During Program/Erase
8.4.3.2 Program/Erase Verification
8.4.3.3 Program/Erase Sequence
Data Sheet
110
The FLASH EEPROM allows a byte or aligned word read/write in one bus cycle.
Misaligned word read/write require an additional bus cycle. The FLASH EEPROM
array responds to read operations only. Write operations are ignored.
An unprogrammed FLASH EEPROM bit has a logic state of 1. A bit must be
programmed to change its state from 1 to 0. Erasing a bit returns it to a logic 1. The
FLASH EEPROM has a minimum program/erase life of 100 cycles. Programming
or erasing the FLASH EEPROM is accomplished by a series of control register
writes and a write to a set of programming latches.
Programming is restricted to a single byte or aligned word at a time determined by
internal signals SZ8 and ADDR0. The FLASH EEPROM must first be completely
erased prior to programming final data values. It is possible to program a location
in the FLASH EEPROM without erasing the entire array, if the new value does not
require the changing of bit values from 0 to 1.
During program or erase operations, read and write accesses may be different
from those during normal operation and are affected by the state of the control bits
in the FLASH EEPROM control register (FEECTL). The next write to any valid
address to the array after LAT is set will cause the address and data to be latched
into the programming latches. Once the address and data are latched, write
accesses to the array will be ignored while LAT is set. Writes to the control registers
will occur normally.
When programming or erasing the FLASH EEPROM array, a special verification
method is required to ensure that the program/erase process is reliable and also to
provide the longest possible life expectancy. This method requires stopping the
program/erase sequence at periods of t
if the FLASH EEPROM is programmed/erased. After the location reaches the
proper value, it must continue to be programmed/erased with additional margin
pulses to ensure that it will remain programmed/erased. Failure to provide the
margin pulses could lead to corrupted or unreliable data.
To begin a program or erase sequence, the external V
and stabilized. The ERAS bit must be set or cleared, depending on whether a
program sequence or an erase sequence is to occur. The LAT bit will be set to
cause any subsequent data written to a valid address within the FLASH EEPROM
to be latched into the programming address and data latches. The next FLASH
FLASH EEPROM
PPULSE
(t
EPULSE
FP
M68HC12B Family — Rev. 8.0
for erasing) to determine
voltage must be applied
MOTOROLA