XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 72
XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
(362 pages)
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Resets and Interrupts
4.5 Interrupt Control and Priority Registers
4.5.1 Interrupt Control Register
Data Sheet
72
never start the interrupt service sequence only to determine that there is no longer
an interrupt source. In the event that this does occur, the trap vector will be taken.
If IRQ is selected as an edge-triggered interrupt, the hold time of the level after the
active edge is independent of when the interrupt is serviced. As long as the
minimum hold time is met, the interrupt will be latched inside the MCU. In this case,
the IRQ edge interrupt latch is cleared automatically when the interrupt is serviced.
All of the remaining interrupts are latched by the MCU with a flag bit. These
interrupt flags should be cleared during an interrupt service routine or when the
interrupts are masked by the I bit. By doing this, the MCU will never get an unknown
interrupt source and take the trap vector.
This section describes the interrupt control and priority registers.
Read: Anytime
Write: Varies from bit to bit
IRQE — IRQ Edge-Sensitive Only Bit
IRQEN — External IRQ Enable Bit
DLY — Oscillator Startup Delay on Exit from Stop Mode Bit
IRQE can be written once in normal modes. In special modes, IRQE can be
written anytime, but the first write is ignored.
IRQEN can be written anytime in all modes. The IRQ pin has an internal pullup.
DLY can be written once in normal modes. In special modes, DLY can be written
anytime.
The delay time of about 4096 cycles is based on the E-clock rate.
Address: $001E
Reset:
Read:
Write:
1 = IRQ pin responds only to falling edges.
0 = IRQ pin responds to low levels.
1 = IRQ pin connected to interrupt logic
0 = IRQ pin disconnected from interrupt logic
1 = Stabilization delay on exit from stop mode
0 = No stabilization delay on exit from stop mode
IRQE
Bit 7
0
Figure 4-1. Interrupt Control Register (INTCR)
IRQEN
Resets and Interrupts
6
1
DLY
5
1
4
0
0
3
0
0
M68HC12B Family — Rev. 8.0
2
0
0
1
0
0
MOTOROLA
Bit 0
0
0
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