XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 171

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

13.3.2 Pulse Accumulators
13.3.2.1 Pulse Accumulator Latch Mode
13.3.2.2 Pulse Accumulator Queue Mode
M68HC12B Family — Rev. 8.0
MOTOROLA
IC Queue Mode (see
Four 8-bit pulse accumulators with four 8-bit holding registers are associated with
the four IC buffered channels. See
number of active edges at the input of its channel.
The user can prevent 8-bit pulse accumulators from counting further than $FF by
PACMX control bit in input control system control register (ICSYS). In this case, a
value of $FF means that 255 counts or more have occurred.
Each pair of pulse accumulators can be used as a 16-bit pulse accumulator.
See
For more information on the two modes of operation for the pulse accumulators,
see
Queue
The value of the pulse accumulator is transferred to its holding register when the
modulus down-counter reaches zero, a write $0000 to the modulus counter, or
when the force latch control bit ICLAT is written. At the same time, the pulse
accumulator is cleared.
When queue mode is enabled, reads of an input capture holding register will
transfer the contents of the associated pulse accumulator to its holding register. At
the same time, the pulse accumulator is cleared.
•
When enabled (LATQ = 0), the main timer value is memorized in the IC register
by a valid input pin transition.
•
•
In queue mode, reads of the holding register will latch the corresponding pulse
accumulator value to its holding register.
13.3.2.1 Pulse Accumulator Latch Mode
Figure
new value. In case of latching, the contents of its holding register are
overwritten.
If the corresponding NOVWx bit of the ICOVW register is set, the capture
register or its holding register cannot be written by an event unless they are
empty (see
overwritten until it is read or latched in the holding register.
If the corresponding NOVWx bit of the ICOVW register is cleared, with a new
occurrence of a capture, the value of the IC register will be transferred to its
holding register and the IC register memorizes the new timer value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture
register or its holding register cannot be written by an event unless they are
empty (see
Mode.
13-4.
Enhanced Capture Timer (ECT) Module
13.3.1 IC
13.3.1 IC
Figure
Channels). This will prevent the captured value to be
Channels).
13-2):
Figure
Enhanced Capture Timer Modes of Operation
13-3. A pulse accumulator counts the
Enhanced Capture Timer (ECT) Module
and
13.3.2.2 Pulse Accumulator
Data Sheet
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