HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1016

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
H8S/2639, H8S/2638, H8S/2636,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
H8S/2630, H8S/2635 Group
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
23B.5.2 Usage Notes
Note: The DTC is not implemented in the H8S/2635 Group.
DTC Module Stop: Depending on the operating status of the DTC, the MSTPA7 and MSTPA6
bits may not be set to 1. Setting of the DTC module stop mode should be carried out only when
the respective module is not activated.
For details, refer to section 8, Data Transfer Controller (DTC).
On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in
module stop mode. Consequently, if module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
Writing to MSTPCR: MSTPCR should only be written to by the CPU.
23B.6 Software Standby Mode
23B.6.1 Software Standby Mode
A transition is made to software standby mode when the SLEEP instruction is executed when the
SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT1) PSS bit = 0. In
this mode, the CPU, on-chip supporting modules, and oscillator all stop * . However, the contents
of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than
the SCI, A/D converter, Motor control PWM, HCAN and I/O ports, are retained. Whether the
address bus and bus control signals are placed in the high-impedance state.
In this mode the oscillator stops * , and therefore power dissipation is significantly reduced.
Note: * The subclock (φSUB) operates if the SUBSTP bit in LPWRCR is set to 0.
Page 966 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010