HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1401
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
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H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
TIOR5—Timer I/O Control Register 5
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Bit
Initial value
Read/Write
TGR5B I/O Control
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
IOB3
R/W
TGR5B is
output
compare
register
TGR5B is
input
capture
register
7
0
TGR5A I/O Control
0
1
IOB2
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCB5 pin
R/W
6
0
0
1
*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
IOB1
R/W
TGR5A is
output
compare
register
TGR5A is
input
capture
register
5
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
IOB0
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCA5 pin
R/W
4
0
H'FEA2
IOA3
R/W
3
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
*: Don't care
IOA2
R/W
2
0
Appendix B Internal I/O Register
IOA1
R/W
1
0
*: Don't care
Page 1351 of 1458
IOA0
R/W
0
0
TPU5
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