HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1370

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix B Internal I/O Register
BCRA—Break Control Register A
BCRB—Break Control Register B
Page 1320 of 1458
Notes: 1. The bit configuration of BCRB is the same as for BCRA.
Condition Match Flag A
Bit
Initial value
Read/Write
0 [Clearing condition]
1
• When 0 is written to CMFA after reading CMFA = 1
[Setting condition]
• When a condition set for channel A is satisfied
CPU Cycle/DTC Cycle Select A
0 PC break is performed when CPU is bus master
1
2. These registers are not available in the H8S/2635 Group.
* Only a 0 may be written to this bit to clear the flag.
PC break is performed when CPU or DTC is bus master
Break Address Mask Register
0
1
R/(W)*
CMFA
0
1
0
1
7
0
0
1
0
1
0
1
0
1
Break Condition Select
0
1
All BARA bits are unmasked and included in break conditions
BAA0 (lowest bit) is masked, and not included in break conditions
BAA1, BAA0 (lower 2 bits) are masked, and not included in break conditions
BAA2 to BAA0 (lower 3 bits) are masked, and not included in break conditions
BAA3 to BAA0 (lower 4 bits) are masked, and not included in break conditions
BAA7 to BAA0 (lower 8 bits) are masked, and not included in break conditions
BAA11 to BAA0 (lower 12 bits) are masked, and not included in break conditions
BAA15 to BAA0 (lower 16 bits) are masked, and not included in break conditions
CDA
R/W
0
1
0
1
6
0
Data read/write cycle is used as break condition
Instruction fetch is used as break condition
Data read cycle is used as break condition
Data write cycle is used as break condition
BAMRA2
R/W
5
0
BAMRA1
R/W
4
0
BAMRA0
R/W
3
0
Break Interrupt Enable
H'FE08
H'FE09
0 PC break interrupts are disabled
1
CSELA1
PC break interrupts are enabled
R/W
2
0
CSELA0
R/W
H8S/2639, H8S/2638, H8S/2636,
1
0
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
BIEA
R/W
0
0
May 28, 2010
PBC
PBC