HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 637

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
15.3.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal.
The slave device compares its own address with the slave address in the first frame following the
establishment of the start condition issued by the master device. If the addresses match, the slave
device operates as the slave device designated by the master device.
Figure 15-14 is a flowchart showing an example of slave receive mode operation.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing
Figure 15-13 Example of Master Receive Mode Stop Condition Generation Timing
Slave Receive Operation
Data 2
Bit 0
8
[6] IRIC clearance
[4] IRTR = 0
[3]
Data 1
A
[8]
1 clock cycle wait time
[4] IRTR = 1
9
[7] ACKB set to 1
[3]
Bit 7
[9] TRS set to 1
1
(MLS = ACKB = 0, WAIT = 1)
Data 2
[10] ICDR read (data 2)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
[11] IRIC clearance
3
4
Data 3
5
6
7
(Only for the H8S/2638, H8S/2639, and H8S/2630)
[14] IRIC clearance
8
[15] WAIT cleared to 0
[13] IRTR = 0
[12]
IRIC clearance
Section 15 I
A
[13] IRTR = 1
[12]
9
[16] ICDR read (data 3)
Data 3
2
C Bus Interface [Option]
[17] Stop condition
issued
Page 587 of 1458
Stop condition
generated

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