HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 601

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2
H8S/2639, H8S/2638, H8S/2636,
Section 15 I
C Bus Interface [Option]
H8S/2630, H8S/2635 Group
(Only for the H8S/2638, H8S/2639, and H8S/2630)
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or
written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the three
registers are performed automatically in coordination with changes in the bus state, and affect the
status of internal flags such as TDRE and RDRF.
If IIC is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following
transmission/reception of one frame of data using ICDRS, data is transferred automatically from
ICDRT to ICDRS. If IIC is in receive mode and no previous data remains in ICDRR (the RDRF
flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred
automatically from ICDRS to ICDRR.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
ICDR is assigned to the same address as SARX, and can be written and read only when the ICE
bit is set to 1 in ICCR.
The value of ICDR is undefined after a reset.
The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the
TDRE and RDRF flags affects the status of the interrupt flags.
REJ09B0103-0800 Rev. 8.00
Page 551 of 1458
May 28, 2010