HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1446
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Part Number
Manufacturer
Quantity
Price
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Part Number:
HD64F2638F20J
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PENESAS
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Appendix B Internal I/O Register
Notes: 1. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,
TDR0—Transmit Data Register 0
Page 1396 of 1458
Bit
Initial value
Read/Write
2. RXI and ERI interrupt request cancellation can be performed by reading 1 from the
3. The TDRE flag in SSR is fixed at 1.
4. In this state, serial transmission is started when transmit data is written to TDR and the
5. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
6. Serial reception is started in this state when a start bit is detected in asynchronous
7. When receive data including MPB = 0 is received, receive data transfer from RSR to
8. TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then
then clearing it to 0, or clearing the TIE bit to 0.
RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the
RIE bit to 0.
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transfer format before setting the TE bit
to 1.
retain their states.
mode or serial clock input is detected in clocked synchronous mode.
SMR setting must be performed to decide the transfer format before setting the RE bit
to 1.
RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR ,
is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR
is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI
interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag
setting is enabled.
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
R/W
7
1
R/W
6
1
R/W
5
1
Store serial transmit data
R/W
4
1
H'FF7B
R/W
3
1
SCI0, Smart Card Interface 0
R/W
2
1
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
R/W
1
1
R/W
May 28, 2010
0
1
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