HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1024

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
H8S/2639, H8S/2638, H8S/2636,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
H8S/2630, H8S/2635 Group
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
23B.10 Subactive Mode (U-Mask, W-Mask Version, H8S/2635 Group Only)
23B.10.1 Subactive Mode
When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1,
LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to
subactive mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1, a
transition is made to subactive mode. And if an interrupt occurs in subsleep mode, a transition is
made to subactive mode.
In subactive mode, the CPU operates at low speed on the subclock, and the program is executed
step by step. Supporting modules other than WDT0, and WDT1 are also stopped.
When operating the CPU in subactive mode, the SCKCR SCK2 to SCK0 bits must be set to 0.
23B.10.2 Exiting Subactive Mode
Subactive mode is exited by the SLEEP instruction or the RES or STBY pins.
(1) Exiting Subactive Mode by SLEEP Instruction
When the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit =
0, and TCSR (WDT1) PSS bit = 1, the CPU exits subactive mode and a transition is made to
watch mode. When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR
LSON bit = 1, and TCSR (WDT1) PSS bit = 1, a transition is made to subsleep mode. Finally,
when the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1,
LSON bit = 0, and TCSR (WDT1) PSS bit = 1, a direct transition is made to high-speed mode
(SCK0 to SCK2 all 0).
See section 23B.11, Direct Transitions for details of direct transitions.
(2) Exiting Subactive Mode by RES Pins
For exiting subactive mode by the RES pins, see, Claering with the RES pins in section 23B.6.2,
Clearing Software Standby Mode.
(3) Exiting Subactive Mode by STBY Pin
When the STBY pin level is driven Low, a transition is made to hardware standby mode.
Page 974 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010