HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 199
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Manufacturer
Quantity
Price
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Part Number:
HD64F2638F20J
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PENESAS
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H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
7.1
The chip has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas. The bus specifications, such as bus width and number of access states, can be set
independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU, and data transfer controller (DTC).
Note: The DTC is not implemented in the H8S/2635 Group.
7.1.1
The features of the bus controller are listed below.
• Manages external address space in area units
• Basic bus interface
• Burst ROM interface
• Idle cycle insertion
• Write buffer functions
• Bus arbitration function
• Other features
REJ09B0103-0800 Rev. 8.00
May 28, 2010
⎯ Manages the external space as 8 areas of 2-Mbytes
⎯ Bus specifications can be set independently for each area
⎯ Burst ROM interface can be set
⎯ 8-bit access or 16-bit access can be selected for each area
⎯ 2-state access or 3-state access can be selected for each area
⎯ Program wait states can be inserted for each area
⎯ Burst ROM interface can be set for area 0
⎯ Choice of 1- or 2-state burst access
⎯ An idle cycle can be inserted in case of an external read cycle between different areas
⎯ An idle cycle can be inserted in case of an external write cycle immediately after an
⎯ External write cycle and internal access can be executed in parallel
⎯ Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC
⎯ External bus release function
external read cycle
Overview
Features
Section 7 Bus Controller
Section 7 Bus Controller
Page 149 of 1458
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