HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 534
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Quantity
Price
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Section 13 Serial Communication Interface (SCI)
In serial reception, the SCI operates as described below.
[1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal
[2] The received data is stored in RSR in LSB-to-MSB order.
[3] The parity bit and stop bit are received.
Note: * Subsequent receive operations cannot be performed when a receive error has occurred.
[4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt
Page 484 of 1458
synchronization and starts reception.
After receiving these bits, the SCI carries out the following checks.
[a] Parity check:
[b] Stop bit check:
[c] Status check:
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in
RDR.
If a receive error * is detected in the error check, the operation is as shown in table 13-11.
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a
receive error interrupt (ERI) request is generated.
The SCI checks whether the number of 1 bits in the receive data agrees with the parity
(even or odd) set in the O/E bit in SMR.
The SCI checks whether the stop bit is 1.
If there are two stop bits, only the first is checked.
The SCI checks whether the RDRF flag is 0, indicating that the receive data can be
transferred from RSR to RDR.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be
cleared to 0.
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
May 28, 2010
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