HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 735

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
17.2
17.2.1
Bit
Initial value
R/W
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion.
The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected
channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte
(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and
stored. Bits 5 to 0 are always read as 0.
The correspondence between the analog input channels and ADDR registers is shown in
table 17-3.
ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower
byte, data transfer is performed via a temporary register (TEMP). For details, see section 17.3,
Interface to Bus Master.
The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop
mode.
Table 17-3 Analog Input Channels and Corresponding ADDR Registers
Group 0
AN0
AN1
AN2
AN3
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Channel Set 0 (CH3 = 0)
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
:
:
:
AD9
Group 1
AN4
AN5
AN6
AN7
15
R
0
AD8
14
R
0
Analog Input Channel
AD7
13
R
0
AD6
12
R
0
Group 0
AN8
AN9
AN10
AN11
AD5
11
R
0
Channel Set 1 (CH3 = 1)
AD4
10
R
0
AD3
R
9
0
Group 1
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
AD2
R
8
0
AD1
R
7
0
AD0
R
6
0
⎯
R
5
0
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
⎯
R
4
0
Section 17 A/D Converter
⎯
R
3
0
⎯
R
2
0
Page 685 of 1458
⎯
R
1
0
⎯
R
0
0