HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 467

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
11.3.4
Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 11-6 shows a sample
procedure for setting up non-overlapping pulse output.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained
without imposing a load on the CPU.
PPG setup
TPU setup
TPU setup
Figure 11-6 Setup Procedure for Non-Overlapping Pulse Output (Example)
Non-Overlapping Pulse Output
Set non-overlapping groups
Set counting operation
Select interrupt request
Set initial output data
Select TGR functions
Select output trigger
Enable pulse output
Compare match?
Non-overlapping
Set TGR values
Set next pulse
Set next pulse
Start counter
PPG output
output data
output data
Yes
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[1] Set TIOR to make TGRA and
[2] Set the pulse output trigger period
[3] Select the counter clock source
[4] Enable the TGIA interrupt in TIER.
[5] Set the initial output values in
[6] Set the DDR and NDER bits for the
[7] Select the TPU compare match
[8] In PMR, select the groups that will
[9] Set the next pulse output values in
[10] Set the CST bit in TSTR to 1 to
[11] At each TGIA interrupt, set the next
Section 11 Programmable Pulse Generator (PPG)
TGRB an output compare registers
(with output disabled)
in TGRB and the non-overlap
margin in TGRA.
with bits TPSC2 to TPSC0 in TCR.
Select the counter clear source
with bits CCLR1 and CCLR0.
The DTC can also be set up to
PODR.
pins to be used for pulse output to
1.
event to be used as the pulse
output trigger in PCR.
operate in non-overlap mode.
NDR.
start the TCNT counter.
output values in NDR.
transfer data to NDR.
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