HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 194
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Quantity
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Section 6 PC Break Controller (PBC)
6.3.2
(1) Initial settings
(2) Satisfaction of break condition
(3) Interrupt handling
6.3.3
(1) The PC break interrupt is shared by channels A and B. The channel from which the request
(2) The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB
(3) A PC break interrupt generated when the DTC is the bus master is accepted after the bus has
Page 144 of 1458
⎯ Set the break address in BARA. For a PC break caused by a data access, set the target
⎯ Set the break conditions in BCRA.
⎯ After execution of the instruction that performs a data access on the set address, a PC break
⎯ After priority determination by the interrupt controller, PC break interrupt exception
was issued must be determined by the interrupt handler.
after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be
requested after interrupt handling ends.
been transferred to the CPU by the bus controller.
ROM, RAM, I/O, or external address space address as the break address. Stack operations
and branch address reads are included in data accesses.
BCRA bit 6 (CDA): Select the bus master.
BCRA bits 5 to 3 (BAMA2 to BAMA0): Set the address bits to be masked.
BCRA bits 2, 1 (CSELA1, CSELA0): Set 01, 10, or 11 to specify data access as the break
condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
request is generated and the condition match flag (CMFA) is set.
handling is started.
PC Break Interrupt Due to Data Access
Notes on PC Break Interrupt Handling
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
May 28, 2010
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