HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1432
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
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252
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Appendix B Internal I/O Register
TSR2—Timer Status Register 2
Page 1382 of 1458
Note: * Can only be written with 0 for flag clearing.
Bit
Initial value
Read/Write
Count Direction Flag
0
1
TCNT counts down
TCNT counts up
Underflow Flag
TCFD
0
1
R
7
1
[Clearing condition]
• When 0 is written to TCFU after reading TCFU = 1
[Setting condition]
• When the TCNT value underflows (changes from H'0000 to H'FFFF)
Overflow Flag
0
1
[Clearing condition]
• When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
• When the TCNT value overflows (changes from H'FFFF to H'0000)
⎯
⎯
6
1
Input Capture/Output Compare Flag B
0
1
[Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as output compare register
• When TCNT value is transferred to TGRB by input capture signal while
R/(W)*
TGRB is functioning as input capture register
TCFU
5
0
Input Capture/Output Compare Flag A
0
1
R/(W)*
TCFV
[Clearing conditions]
• When DTC is activated by TGIA interrupt while DISEL bit
• When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is functioning as output
• When TCNT value is transferred to TGRA by input capture
4
0
of MRB in DTC is 0
compare register
signal while TGRA is functioning as input capture register
H'FF35
⎯
⎯
3
0
⎯
⎯
2
0
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
R/(W)*
H8S/2630, H8S/2635 Group
TGFB
1
0
R/(W)*
TGFA
May 28, 2010
0
0
TPU2
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