MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 102

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

System Integration Block (SIB)
HWT—Hardware Watchdog Timeout
WPV—Write Protect Violation
ADC—Address Decode Conflict
3.8.3 System Control Bits
The system control logic uses six control bits in the SCR.
WPVE—Write Protect Violation Enable
3-52
This bit is set when the hardware watchdog (see 3.8.6 Hardware Watchdog) reaches the
end of its time interval; BERR is generated following the watchdog timeout, even if this bit
is already set.
This bit is set when a bus master attempts to write to a location that has RW set to zero
(read only) in its associated base register (BR3–BR0). Provided WPVE (bit 20) is set,
BERR will be asserted on the bus cycle that sets this bit. If WPV and WPVE are both set
when a write protect violation occurs, BERR will still be generated.
This bit is set when a conflict has occurred in the chip-select logic because two or more
chip-select lines attempt assertion in the same bus cycle. This conflict may be caused by
a programming error in which the user-allocated memory areas for each chip select over-
lap each other. Provided ADCE (bit 17) is set, the occurrence of ADC will cause BERR to
be asserted. If this bit is already set when another address decode conflict occurs, BERR
will still be generated. The chip-select logic will protect the IMP from issuing two simulta-
neous chip selects by employing a priority system.
After system reset, this bit defaults to zero.
0 = BERR is not asserted when a write protect violation occurs.
1 = BERR is asserted when a write protect violation occurs.
this happens and that other pending interrupts at the same orig-
inal priority level also execute with BCLR continuously asserted,
the following technique may be used. Using a parallel I/O line
connected to the IRQ1 line, the original priority level interrupt
toggles this I/O line just before it executes the RTE instruction,
causing a request for a level 1 interrupt. Since this is the lowest
interrupt level, this routine will not be executed until all other
pending interrupt routines have executed. Then in the level 1 in-
terrupt routine, the IPA bit in the SCR is cleared.
Regardless of the state of the chip-select programming, this bit
will not be set and BERR will not be asserted for an address de-
code conflict occurring during access to a system configuration
register. This is provided to guarantee access to the system con-
figuration registers (BAR and SCR) during initialization.
MC68302 USER’S MANUAL
NOTE
MOTOROLA