MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 274
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
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Signal Description
BCLR—Bus Clear
5.8 BUS ARBITRATION PINS
The bus arbitration pins are shown in Figure 5-8.
BR—Bus Request
BG—Bus Grant
BGACK—Bus Grant Acknowledge
5-10
This open-drain output indicates that the M68000 core or the serial DMA (SDMA) requests
the external bus master to release the bus. The core may be configured to assert this sig-
nal when it has a pending interrupt to execute. The SDMA asserts this signal when one
of the SCCs is requesting DMA service.
When the M68000 core is disabled, this signal is an input to the independent DMA (IDMA)
and is interpreted as a bus release request. It remains an output from the SDMA in this
mode.
This input signal indicates to the on-chip bus arbiter that an external device desires to be-
come the bus master. See 3.8.5.2 External Bus Arbitration for details. This signal is an
open-drain output request signal from the IDMA and SDMA when the internal M68000
core is disabled.
This output signal indicates to all external bus master devices that the processor will re-
lease bus control at the end of the current bus cycle to an external bus master. This signal
is an input to the IDMA and SDMA when the internal M68000 core is disabled. During total
system reset, BG = BR.
This bidirectional signal indicates that some other device besides the M68000 core has
become the bus master. This signal is an input when an external device or the M68000
core owns the bus. This signal is an output when the IDMA or SDMA has become the
master of the bus. If the SDMA steals a cycle from the IDMA, the BGACK pin will remain
asserted continuously.
BGACK should always be used in the external bus arbitration
process. See 3.8.5.2 External Bus Arbitration for details.
Figure 5-8. Bus Arbitration Pins
MC68302 USER’S MANUAL
MC68302
NOTE
BR
BG
BGACK
MOTOROLA
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