MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 458

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

SCC Programming Reference
BIT 15—Reserved for future use; should be written with zero.
EXSYN—External Sync
NTSYN—No Transmit SYNC
REVD—Reverse Data
Bits 11-6—Reserved for future use; should be written with zero.
DIAG1, DIAG0—Diagnostic Mode
ENR—Enable Receiver
ENT—Enable Transmitter
MODE1, MODE0—Channel Mode
E.3.1.2.3 SCC Data Synchronization Register (DSR). This 16-bit register is located at off-
set $886 (SCC1), $896 (SCC2), and $8A6 (SCC3). The DSR specifies the pattern used for
the receive frame synchronization procedure if the EXSYN bit is cleared. For transparent,
the DSR may be set to any desired pattern. The DSR value after reset is $7E7E.
E.3.1.2.4 Transparent Event Register (SCCE). This 8-bit register is located at offset $888
(SCC1), $898 (SCC2), and $8A8 (SCC3) on D15-D8 of a 16-bit data bus. The SCCE is used
to report events recognized by the transparent channel. Bits must be cleared by the user to
avoid missing interrupt events. Bits are cleared by writing ones to the corresponding bit posi-
tions
E-36
15
When set, the SCC receiver uses the L1SY1/CD1, CD2, or CD3 pins to synchronize the
receiver and transmitter to the beginning of a transparent frame.
This bit must be set for the SCC to operate in the transparent mode.
When this bit is set, the receiver and transmitter will reverse the character bit order, trans-
mitting the most significant bit first.
00 = Normal operation.
01 = Loopback mode.
10 = Automatic echo.
11 = Software operation.
0 = Receiver is disabled.
1 = Receiver is enabled
0 = Transmitter is disabled.
1 = Transmitter is enabled.
00 = HDLC.
01 = Asynchronous (UART and DDCMP).
10 = Synchronous DDCMP and V.110.
11 = BISYNC and Promiscuous (Transparent).
SYN2
MC68360 USER’S MANUAL
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SYN1
MOTOROLA
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