MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 182
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
Communications Processor (CP)
X—External Buffer
W—Wrap (Final BD in Table)
I—Interrupt
Bits 8–1—Reserved for future use.
CR—Clear-to-Send Report
A—Address
P—Preamble
The following bits are written by the CP after it has finished transmitting the associated data
buffer.
4-62
This bit allows a choice of no delay between buffers transmitted in UART mode, versus a
more accurate CTS lost error reporting and two bits of idle between buffers.
If the DIAG1–DIAG0 bits in the SCM are set to software operation (rather than normal op-
eration), then this bit only affects the delay between buffers, not the CTS reporting, and
would normally be set to zero.
0 = The buffer associated with this BD is in internal dual-port RAM.
1 = The buffer associated with this BD is in external memory.
0 = This is not the last BD in the Tx BD table.
1 = This is the last BD in the Tx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been serviced.
1 = The TX bit in the UART event register will be set when this buffer has been serviced
0 = The buffer following this buffer will be transmitted with no delay (assuming it is
1 = Normal CTS lost (CT bit) error reporting, and two bits of idle occur between back-
This bit is valid only in multidrop mode (UM0 = 1).
0 = This buffer contains data only.
1 = Set by the M68000 core, this bit indicates that this buffer contains address charac-
0 = No preamble sequence is sent.
1 = The UART sends one preamble sequence (9 to 13 ones) before sending the data.
transmit data from the first BD in the table.
by the CP, which can cause an interrupt.
ready), but the CT bit may not be set in the correct Tx BD, or may not be set at all
in a CTS lost condition. The user is advised to monitor the CTS bit in the UART
event register for an indication of CTS lost, in addition to the CT bits in the Tx BDs.
The CTS bit will always be set properly.
to-back buffers.
ter(s). All the buffer's data will be transmitted as address characters.
The user is required to set the wrap bit in one of the first eight
BDs; otherwise, errant behavior may occur.
MC68302 USER’S MANUAL
NOTE
MOTOROLA
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