MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 159
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
More than one bit may be cleared at a time. This register is cleared at reset (total system
reset, CP reset, or the M68000 RESET instruction).
4.5.8.2 SCC Mask Register (SCCM)
This 8-bit read-write register allows enabling or disabling interrupt generation by the CP for
specific events in each SCC channel. An interrupt will only be generated if the SCC inter-
rupts for this channel are enabled in the IMR in the interrupt controller.
If a bit in the SCC mask register is zero, the CP will not proceed with its usual interrupt han-
dling whenever that event occurs. Any time a bit in the SCC mask register is set, a one in
the corresponding bit in the SCC event register will cause the SCC event bit in the IPR to be
set.
The bit locations in the SCC mask register are identical to those in the SCC event register.
SCCM is cleared upon reset.
4.5.8.3 SCC Status Register (SCCs)
Each SCCS reflects line status for that SCC. It is used primarily in the NMSI physical inter-
face mode to read the current status of the CTS pin, the CD pin, and idle status of the RXD
pin. This 8-bit read-only register may be read at any time.
The CTS status indication in the SCCS is not valid until after the SCC transmitter is enabled
(ENT bit is set). After this, the CTS indication will only be updated in the SCCS when any
change in its condition is sampled by a rising edge of TCLK. The CD and ID status indica-
tions are not valid until the SCC receiver is enabled (ENR bit is set). After this, the CD and
ID indications will only be updated in the SCCS when any change in their condition is sam-
pled by a rising edge of RCLK.
Beyond what the SCCS provides, in the BDs for each protocol, indications are given as to
whether the status of these signals has changed during the reception/transmission of a giv-
en buffer. Furthermore, in the event registers (SCCE) for each protocol, a maskable interrupt
bit is provided to allow the detection of any change in signal status.
MOTOROLA
Bit manipulation instructions such as BSET should not be used
to clear bits in the event register because any bits that were set
will be written back as ones (thus clearing all pending interrupts)
as well as the desired bit.
Since the RISC controller is involved in the update process, a
slight delay between the external line condition change and the
update of the SCCS is induced.
After power-on reset, when the SCC is enabled for the first time,
the SCCE register will show that a change of status occurred, re-
MC68302 USER’S MANUAL
NOTE
NOTE
NOTE
Communications Processor (CP)
4-39
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