MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 226

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
DSOH—DDCMP SOH Register
DENQ—DDCMP ENQ Register
DDLE—DDCMP DLE Register
The 8-bit DDLE register is used to synchronize maintenance messages by the DDCMP con-
troller. When the DDCMP controller is not in hunt mode (byte synchronization is estab-
lished), it searches for the DLE character to start processing the maintenance messages.
The DDCMP controller transfers the header and the data fields of the message to the buffer,
checks the header and data CRCs, counts the data field up to the value contained in the
header byte count field, and compares the header address field against the user-defined ad-
dresses. The DDLE register is a memory-mapped read-write register.
4.5.14.7 DDCMP Address Recognition.
Each DDCMP controller has five 16-bit registers to support address recognition: one mask
register and four address registers (DMASK, DADDR1, DADDR2, DADDR3, and DADDR4).
The DDCMP controller reads the message address from the receiver, masks it with the user-
defined DMASK bits, and then checks the result against the four address register values. A
one in DMASK indicates a bit position where a comparison should take place; a zero masks
the comparison. For 8-bit address comparison, the high byte of DMASK should be zero.
4.5.14.8 DDCMP Error-Handling Procedure
The DDCMP controller reports message reception and transmission errors using the chan-
nel BDs, the error counters, and the DDCMP event register. The modem interface lines can
also be directly monitored with the SCC status register.
Transmission errors:
4-106
The 8-bit DSOH register is used to synchronize data messages by the DDCMP controller.
When the DDCMP controller is not in hunt mode (byte synchronization is now estab-
lished), it searches for the SOH character to start processing data messages. The DDC-
MP controller transfers the header and the data fields of the message to the buffer, checks
the header and data CRCs, counts the data field up to the value contained in the header
byte count field, and compares the header address field against the user-defined address-
es. The DSOH register is a memory-mapped read-write register.
The 8-bit DENQ register is used to synchronize control messages by the DDCMP control-
ler. When the DDCMP controller is not in hunt mode (byte synchronization is established),
it searches for the ENQ character to start processing control messages. The DDCMP con-
troller transfers the message to the buffer, checks the CRC, and compares the message
address field against the user-defined addresses. The DENQ register is a memory-
mapped read-write register.
1. Transmitter Underrun. When this error occurs, the channel terminates buffer transmis-
sion, closes the buffer, sets the underrun (UN) bit in the BD, and generates the trans-
mit error (TXE) interrupt (if enabled). The channel will resume transmission after the
reception of the RESTART TRANSMIT command. The FIFO size is three bytes.
MC68302 USER’S MANUAL
MOTOROLA