MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 68
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
System Integration Block (SIB)
Dedicated Mode
All INRQ and EXRQ sources are prioritized within the interrupt controller. The M68000 sup-
ports seven priority levels. Level 7, the highest priority level, is nonmaskable. EXRQ sources
are given their own separate priority level. Priority level 4 is reserved exclusively for the
INRQ sources with all the INRQ sources being further prioritized within this level. If more
than one INRQ or EXRQ interrupt request is pending, the interrupt controller presents the
highest priority interrupt to the M68000 core through an internal, hidden set of IPL2–IPL0
lines.
When the M68000 core executes the interrupt acknowledge cycle, a vector must be provid-
ed. If an INRQ source generated the interrupt, the interrupt controller always provides the
vector. If an EXRQ source generated the interrupt, three options are available to generate
the vector.
First, in most cases the interrupt controller can be configured to provide the vector to the
M68000 core. This is usually the preferred solution.
Second, the external peripheral can generate the vector. To assist this process, the interrupt
controller can provide up to three interrupt acknowledge outputs (IACK7, IACK6, and
IACK1).
Third, the external peripheral can assert the autovector (AVEC) pin to cause the M68000 to
use an autovector. The autovector method maps each interrupt level to a fixed vector loca-
tion in the exception vector table, regardless of how many interrupt sources exist at that lev-
el.
To improve interrupt latency timing, a fast interrupt latency technique is supported in the
IMP. On recognition of an interrupt, the IMP can assert the bus clear (BCLR) signal exter-
nally, which can be used to force other bus masters off the bus. This involves the IPA and
BCLM bits in the system control register (see 3.8 System Control).
3.2.2 Interrupt Priorities
INRQ and EXRQ interrupts are assigned to an interrupt priority level. INRQ interrupts are
also assigned relative priorities within their given interrupt priority level. A fully nested inter-
rupt environment is provided so that a higher priority interrupt is serviced before a lower pri-
ority interrupt.
3.2.2.1 INRQ and EXRQ Priority Levels
Seven levels of interrupt priority may be implemented in IMP system designs, with level 7
having the highest priority. INRQ interrupts are assigned to level 4 (fixed). EXRQ interrupts
are assigned by the user to any of the remaining six priority levels in normal mode. In dedi-
cated mode, EXRQ interrupts may be assigned to priority levels 7, 6, and 1.
3-18
In this mode, the three interrupt request pins are configured as IRQ7, IRQ6, and IRQ1 to
provide dedicated request lines for three external sources at priority levels 1, 6, and 7.
Each of these lines may be programmed to be edge-triggered or level-sensitive. In addi-
tion to level 4, which is reserved for INRQ interrupts, interrupt priority levels 2, 3, and 5
must not be assigned to external devices in this mode.
MC68302 USER’S MANUAL
MOTOROLA
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