MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 131

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.4.1 IDL Interface
The IDL interface is a full-duplex ISDN interface used to interconnect a physical layer device
(such as the Motorola ISDN S/T transceiver MC145474) to the integrated multiprotocol pro-
cessor (IMP). Data on five channels (B1, B2, D, A, and M) is transferred in a 20-bit frame
every 125 s, providing 160-kbps full-duplex bandwidth. The IMP is an IDL slave device that
is clocked by the IDL bus master (physical layer device). The IMP provides direct connec-
tions to the MC145474. Refer to Figure 4-6 for the IDL bus signals.
The IMP supports 10-bit IDL as shown in Figure 4-6; it does not support 8-bit IDL.
An application of the IDL interface is to build a basic rate ISDN terminal adaptor (see Figure
4-7). In such an application, the IDL interface is used to connect the 2B + D channels be-
tween the IMP, CODEC, and S/T transceiver. One of the IMP SCCs would be configured to
HDLC mode to handle the D channel; another IMP SCC would be used to rate adapt the
MOTOROLA
L1RXD
Example: B1 supports 2 bits; B2 supports 3 bits
L1RXD
L1CLK
L1TXD
(L1RQ and L1GR not shown)
L1TXD
L1SY1
SIMASK = $26C0; SIMODE = $01B2
THREE-STATE
DON'T CARE
6
SCC1–SCC3
B1
B1
Figure 4-6. IDL Bus Signals
SCC2
MC68302 USER’S MANUAL
B1
B1
2
SCC3
D
D
D
D
1
SMC2
SMC2
A
A
A
A
1
1
SCC1
B2
B2
2
B2
B2
2
Communications Processor (CP)
SCC1
B2
B2
1
2
SCC3
D
D
D
D
1
(CLOCK NOT TO SCALE)
SMC1
SMC1
M
M
M
M
1
4-11