MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 201
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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MC68302EH16CR2
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 201 of 481
- Download datasheet (2Mb)
CTS—Clear-To-Send Status Changed
CD—Carrier Detect Status Changed
MOTOROLA
RXD
CD
HDLC SCCE
NOTES:
LEGEND:
A change in the status of the CTS line was detected on the HDLC channel. The SCC sta-
tus register may be read to determine the current status.
A change in the status of the CD line was detected on the HDLC channel. The SCC status
register may be read to determine the current status.
TXD
RTS
CTS
HDLC SCCE
NOTE: TXB event shown assumes all three bytes were put into a single buffer.
1. RXB event assumes receive buffers are 6 bytes each.
2. The second IDL event occurs after 15 ones are received in a row.
EVENTS
EVENTS
F = Flag A = Address byte C = Control byte I = Information byte CR = CRC byte
TRANSMITTED BY HDLC
RECEIVED IN HDLC
Example shows one additional opening flag. This is programmable.
TIME
FRAME
FRAME
LINE IDLE
CD
Figure 4-29. HDLC Interrupt Events Example
LINE IDLE
CTS
7
IDL
F
CD
A
6
CTS
MC68302 USER’S MANUAL
A
STORED IN RX BUFFER
F
IDL
C
5
F
I
TX BUFFER
STORED IN
A
TXE
I
4
A
I
RXB
C
RXF
CR CR
3
CR CR F
BSY
F
RXF
2
TXB
TXB
1
IDL
Communications Processor (CP)
RXB
CTS
LINE IDLE
0
LINE IDLE
CD
4-81
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