MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 215
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
OFFSET + 0
OFFSET + 2
OFFSET + 4
CR—BCS Error
OV—Overrun
CD—Carrier Detect Lost
Data Length
Rx Buffer Pointer
4.5.13.11 BISYNC Transmit Buffer Descriptor (Tx BD).
Data is presented to the CP for transmission on an SCC channel by arranging it in buffers
referenced by the channel's Tx BD table. The CP confirms transmission (or indicates error
conditions) using the BDs to inform the processor that the buffers have been serviced. The
Tx BD is shown in Figure 4-33.
OFFSET +6
The first word of the Tx BD contains status and control bits. These bits are prepared by the
user before transmission and are set by the CP after the buffer has been transmitted.
MOTOROLA
BCS error (CR) is updated every time a byte is written into the buffer. The CR bit includes
the calculation for the current byte. By clearing the RBCS bit in the BISYNC mode register
within eight serial clocks, the user can exclude the current character from the message
BCS calculation. The data length field may be read to determine the current character's
position.
A receiver overrun occurred during message reception.
The carrier detect signal was negated during message reception.
The data length is the number of octets that the CP has written into this BD's data buffer,
including the BCS (if selected). In BISYNC mode, the data length should initially be set to
zero by the user and is incremented each time a received character is written to the data
buffer.
The receive buffer pointer, which always points to the first location of the associated data
buffer, may be even or odd. The buffer may reside in either internal or external memory.
15
R
The actual buffer size should be greater than or equal to the MR-
BLR.
For correct operation of the function codes, the upper 8 bits of
the pointer must be initialized to zero.
14
X
Figure 4-33. BISYNC Transmit Buffer Descriptor
13
W
12
I
TX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
11
L
MC68302 USER’S MANUAL
TB
10
NOTE
NOTE
9
B
DATA LENGTH
BR
8
TD
7
TR
6
Communications Processor (CP)
—
5
—
4
—
3
—
2
UN
1
4-95
CT
0
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