MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 161
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
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Next, the pointer that caused the bus error can be determined by reading the Rx or Tx inter-
nal data pointer from the parameter's memory map of the particular SCC. Following this bus
error, the CP must be reset with a hardware reset or the setting of the RST bit in the com-
mand register.
An SDMA retry cycle is not indicated with any status information or interrupts.
4.5.9 SCC Transparent Mode
The SCC supports several transparent receive and transmit modes, which vary according
to the protocol being implemented. As used here, transparent means data transparency and
is not the same as the totally transparent (promiscuous) mode described later in 4.5.16
Transparent Controller. The transparent modes for each protocol are as follows:
UART Mode
HDLC Mode
BISYNC Mode
There are two possible ways of recognizing SYNCs. Either the EXSYN bit in the BISYNC
mode register is cleared and a SYNC is defined by the SYN1–SYN2 characters in DSR, or
the EXSYN bit is set and a SYNC is determined by an external SYNC pulse.
When the BISYNC control characters table is empty, the SYNC and DLE stripping is dis-
abled, and the BISYNC controller is in normal nontransparent mode (RTR = 0 in BISYNC
mode register). In this case, the configuration is as follows:
MOTOROLA
4—SCC3 Tx Channel
5—SCC3 Rx Channel
If the normal mode is selected (UM1–UM0 = 00 in the UART mode register) and the con-
trol characters table is empty, then the UART will transfer all received characters to mem-
ory except break and idle characters.
When the HDLC mask register = $0000, the HDLC controller will transfer all received
frames to the receive buffers, including address, control, data, and CRC. The HDLC con-
troller still performs the standard HDLC functions of zero insertion/deletion and flag rec-
ognition.
The BISYNC mode may be used to transparently receive data that is delimited by SYNCs.
To do this, the BISYNC control characters table should be empty, and SYNC/DLE strip-
ping should be disabled. Thereafter, all data following the SYNCs will be received into the
receive buffers.
• If EXSYN in the BISYNC mode register is cleared, then the BISYNC controller transfers
• If EXSYN in the BISYNC mode register is set, then the BISYNC controller transfers all
all characters that follow the SYN1–SYN2 sequence to the receive buffers.
characters that follow the external SYNC pulse to the receive buffers.
The BISYNC controller can reverse the bit order in both modes.
MC68302 USER’S MANUAL
NOTE
Communications Processor (CP)
4-41
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