MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 360
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 360 of 481
- Download datasheet (2Mb)
MC68302 Applications
Process receive data (PRD) shows the next receive BD that will be processed. To process
a buffer, check for errors, move or use the data, and then mark the BD as available for use.
This is the last pointer to move in the receive process.
D.3.4 Initial Conditions
Initially the BDs should be configured like those shown in Figure D-4. All three transmit point-
ers should point to the first transmit BD in the table, and both receive pointers should point
to the first receive BD. Also, the data length fields of all the BDs should be zero for the pur-
poses of the following algorithm.
D.3.5 Transmit Algorithm
Use the following routine to configure new data to be transmitted.
Execute anytime:
D.3.6 Interrupt Routine
When an interrupt occurs in the SCC event register perform the following:
If the interrupt was due to receiving a buffer or frame, perform the following receive process:
D-10
1. Make sure that (NTD -> Ready) = 0. If ready = 1, there is no more room to link in buff-
2. Make sure that the (NTD -> data length) = 0 to prevent overwriting a buffer that has
3. Link in the desired buffer to this BD.
4. Set up the control information in the BD, but do not set the ready bit.
5. Do not allow the confirm transmit process to interrupt the following steps:
6. The confirm process interrupt may now be unmasked.
1. Read the SCC event register.
2. Clear any unmasked bits that will be dealt with in this interrupt routine (write ones to
3. Deal with the general status conditions as desired.
1. While (PRD -> Empty) = 0, do the following:
ers to be transmitted, since there are already eight BDs ahead of the SCC.
not been confirmed.
those bits). Those events normally include receiving a buffer or frame, transmitting a
buffer, getting a transmit error, and any change in general status conditions such as
carrier detect or clear-to-send.
/* Buffer has been filled if Empty = 0*/
a. Set the data length to the exact number of bytes (odd or even) that should be
transmitted from this buffer.
b. Set the ready bit of the BD.
c. Move NTD to point to the next BD. (If the wrap bit is set, point to the first BD.)
a. Check for errors in the BD.
b. The user may or may not want to analyze data in the buffer at this time.
c. Move data out of buffer or change the BD pointer to a new location.
d. Clear out the data length field so that it is zero to start with.
MC68302 USER’S MANUAL
MOTOROLA
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