MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 368

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MC68302 Applications
initialization corresponds to the recommended order described in 4.5.7 SCC Initialization.
The second part is a set of loops waiting for data to arrive to be retransmitted out of the
SCC3. The third part is the SCC3 receive interrupt handler. Transmit interrupts are masked
in this example.
D.4.2 Organization of Buffers
In the MC68302, there is no such thing as an receive register (Rx) or transmit register (Tx).
Rather, a flexible structure called a buffer descriptor (BD) is used. In this example, two Rx
BDs and two Tx BDs are used. Each BD is set up to point to a one-byte location for data.
Thus, the receiver and transmitter are double-buffered. The number of Rx or Tx BDs can be
changed simply by changing the number of BDs initialized in the code (and two other lines
documented in the code). However, using at least two BDs has advantages as noted in the
following paragraphs.
The structure of the buffers is shown in Figure D-6.
To make the application more general, the data buffers were located in external RAM; how-
ever, internal RAM could have been used. Each BD points to just one byte in memory as
shown. Note that the data buffers do not need to be consecutive as shown.
From one to eight BDs may be used for both the transmit and receive operation. Use of eight
BDs for the transmit side of SCC3 requires that the SCP and SMCs not be used. As data
rates increase substantially beyond the 9600 baud of this example, the use of more BDs and
more data bytes per BD becomes justified. Why were two Rx BDs and two Tx BDs chosen
rather than just one each?
D-18
MC68302
Figure D-6. Transmit and Receive BD Tables and Buffers
A2
A0
ONLY 2 OF 8 BDS ARE USED.
SCC3 TRANSMIT BD TABLE
SCC3 RECEIVE BD TABLE
RX BD 0
RX BD 1
TX BD 0
TX BD 1
MC68302 USER’S MANUAL
THESE POINTERS TO KNOW
WHERE TO STORE DATA.
A1
ON-CHIP DMA USES
DATA BUFFERS IN RAM
BYTE
BYTE
BYTE
BYTE
$30002
$30000
$30001
$30003
CPU MOVES
DATA FROM
RX TO TX
BUFFERS IN
THIS CODE.
MOTOROLA