MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 389

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

A nibble register write is made by writing one byte with the following format:
A byte register read is made by writing two bytes with the following format:
Data read from the register will be received during the second transaction.
A nibble register read is made by writing one byte with the following format:
Data read from the register will be received during the second transaction.
D.6.13 Additional IMP To S/T Chip Connections
In addition to the IDL bus and the SCP bus, two discrete signals connect the MC145475 S/
T chip to the MC68302 (see Figure D-17).
Each event can be masked and/or cleared by a write/read operation on the corresponding
register. The IRQ signal can be connected to the IRQ1 pin of the MC68302 to generate a
level 1 interrupt.
MOTOROLA
IRQ —The active-low signal sends an interrupt request from the MC145475 to the
MC68302 core. This is an active-low signal that is asserted when one or more of the fol-
lowing events occurs:
RESET—This active-low signal initializes the MC145475, forces all internal state ma-
chines to the initial state, and forces all internal nibble and byte registers (except BR4 and
— Change in the received information state (INFO n) of the S/T receiver.
— Multiframe reception.
D-channel collision.
7
0
7
1
1
X
A2
A2
1
X
The SCP_EN signal must be asserted prior to each SCP trans-
action and negated after completion.
A1
A1
1
X
A0
A0
X
1
D3
A3
X
X
MC68302 USER’S MANUAL
D2
A2
X
X
D1
A1
X
X
NOTE
D0
A0
X
X
0
0
A3–A0 Address Register
A3–A0 Address Register
A2–A0 Address Register
D3–D0 Data Register
X– Don't Care
X–Don't Care
MC68302 Applications
D-39