MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 115

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TSRCLK1—Three-state RCLK1
DBRG1—Disable BRG1
Bits 10 - 0—Reserved. Should be written with zeros.
3.9.1 Freeze Control
Used to freeze the activity of selected peripherals, FRZ is useful for system debugging pur-
poses. When FRZ is asserted:
MOTOROLA
• The CP main controller freezes its activity on the next clock (CLKO) and will continue
• The IDMA completes any bus cycle that is in progress (after DTACK is asserted) and
• Each timer can be programmed to freeze by setting the appropriate bit in the SCR. After
0 = Normal operation
1 = The RCLK1 pin is three-stated. This option may be used to prevent contention on
0 = Normal operation
1= The BRG1 pin is disabled and is driven high. This option should be chosen if it is
in a frozen state as long as FRZ remains asserted. No new interrupt requests and no
memory accesses (internal or external) will occur, and the main controller will not ac-
cess the serial channels.
releases bus ownership. No further bus cycles will be started as long as FRZ remains
asserted.
a one-clock (CLKO) delay, the selected timers will freeze their activity (count, capture)
as long as FRZ remains asserted.
reduce power. An external pullup should be used if TCLK1 is not driven externally.
TSTCLK1 may be toggled at any time, but the SCC1 transmitter should be disabled
and re-enabled if any dynamic change is made on TSTCLK1 during the operation
of the SCC1 transmitter.
the RCLK1 pin if an external clock is provided to the RCLK1 pin while the SCC1
baud rate generator is output on RCLK1. This option may also be chosen if it is re-
quired to run the SCC1 baud rate generator at high speed (for instance in a high
speed UART application), but the RCLK1 output is not needed, and it is desired to
reduce power. An external pullup should be used if RCLK1 is not driven externally.
TSRCLK1 may be toggled at any time, but the SCC1 receiver should be disabled
and re-enabled if any dynamic change is made on TSRCLK1 during the operation
of the SCC1 receiver.
required to run the SCC1 baud rate generator at high speed, but the BRG1 output
is not needed and it is desired to reduce power. Although DBRG1 may be modified
at any time, the user should note that glitches on BRG1 are not prevented by the
MC68302 when the state of DBRG1 is changed.
Regardless of whether or not the freeze logic is used, FRZ must
be negated during system reset.
MC68302 USER’S MANUAL
NOTE
System Integration Block (SIB)
3-65