MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 245

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

channel. In all three error cases, the reception process will not proceed until synchronization
has once again been achieved.
If the REVD bit in the transparent mode register is set, each data byte will be reversed in its
bit order before it is written to memory.
If the interrupt (I) bit in the Rx BD is set, then the RX bit will be set in the transparent event
register following the reception of the buffer. The RX bit can generate a maskable interrupt.
4.5.16.3 Transparent Memory Map
When configured to operate in transparent mode, the IMP overlays the structure illustrated
in Table 4-11 onto the protocol specific area of that SCC parameter RAM. Refer to 2.8
MC68302 Memory Map for the placement of the three SCC parameter RAM areas and Ta-
ble 4-5 for the other parameter RAM values.
Although there are no transparent-specific parameter RAM locations that must be initialized
by the user, the general SCC parameter RAM must still be initialized (see Table 4-5).
The transparent controller uses the same basic data structure as the other protocol control-
lers. Receive and transmit errors are reported through receive and transmit BDs. The status
of the line is reflected in the SCC status register, and a maskable interrupt is generated upon
each status change.
MOTOROLA
SCC BASE + 9C
SCC BASE + 9E
SCC BASE + A0
SCC BASE + A2
SCC BASE + A4
SCC BASE + A6
SCC BASE + A8
SCC BASE + AA
SCC BASE + AC
SCC BASE + AE
SCC BASE + B0
SCC BASE + B2
SCC BASE + B4
SCC BASE + B6
SCC BASE + B8
SCC BASE + BA
SCC BASE + BC
SCC BASE + BE
Table 4-11. Transparent-Specific Parameter RAM
Address
MC68302 USER’S MANUAL
Name
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
Width
Communications Processor (CP)
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
4-125