MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 307
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
6.11 AC ELECTRICAL SPECIFICATIONS—EXTERNAL MASTER
MOTOROLA
NOTES:
Num.
1. Synchronous specifications above are valid only when SAM = 1 in the SCR.
2. It is required that this signal not be asserted prior to the previous rising CLKO edge (i.e., in the previous clock
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
cycle). It must be recognized by the IMP no sooner than the rising CLKO edge shown in the diagram.
(see Figure 6-10, Figure 6-11, and Figure 6-12)
Address Valid to AS Low
AS Low to Clock High
Clock Low to AS High
AS High to Address Hold Time on Write
AS Inactive Time
UDS/LDS Low to Clock High (see Note 2)
Clock Low to UDS/LDS High
R/W Valid to Clock High (see Note 2)
Clock High to R/W High
AS Low to IAC High
AS High to IAC Low
AS Low to DTACK Low (0 Wait State)
Clock Low to DTACK Low (1 Wait State)
AS High to DTACK High
DTACK High to DTACK High Impedance
Clock High to Data-Out Valid
AS High to Data High Impedance
AS High to Data-Out Hold Time
AS High to Address Hold Time on Read
UDS/LDS Inactive Time
Data-In Valid to Clock Low
Clock Low to Data-In Hold Time
INTERNAL SYNCHRONOUS READ/WRITE CYCLES
Characteristic
MC68302 USER’S MANUAL
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
ASHDTH
t
t
CHRWH
t
DTHDTZ
ASHDOI
RWVCH
ASLDTL
t
t
ASLIAH
ASHIAL
CHDOV
t
ASLCH
CLASH
ASHAH
t
t
ASHDZ
AVASL
CLDTL
ASHAI
CLDIH
CLDIV
t
SLCH
CLSH
ASH
t
SH
16.67 MHz
Min
15
30
40
30
30
15
—
—
—
—
—
—
—
—
—
—
—
0
1
0
0
1
Max
45
45
45
40
40
45
30
45
15
30
45
—
—
—
—
—
—
—
—
—
—
—
Min
12
25
—
33
—
25
—
—
—
—
—
—
—
—
—
25
12
20 MHz
0
1
0
0
1
Electrical Characteristics
Max
40
40
40
35
35
40
25
40
15
25
40
—
—
—
—
—
—
—
—
—
—
—
Min
10
20
27
20
20
10
—
—
—
—
—
—
—
—
—
—
—
25 MHz
0
1
0
0
1
Max
30
30
30
27
27
30
20
30
10
20
30
—
—
—
—
—
—
—
—
—
—
—
Unit
clk
clk
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6-19
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