MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 165
![IC MPU MULTI-PROTOCOL 132-PQFP](/photos/6/76/67684/mc68302eh16c_sml.jpg)
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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MC68302EH16CR2
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10 000
- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 165 of 481
- Download datasheet (2Mb)
(RTS). Other modem lines such as data set ready (DSR) and data terminal ready (DTR) can
be supported through the parallel I/O pins.
The UART consists of separate transmit and receive sections whose operations are asyn-
chronous with the M68000 core and may be either synchronous or asynchronous with re-
spect to each other. Each clock can be supplied either from the baud rate generator or from
the external pins.
The UART key features are as follows:
4.5.11.1 Normal Asynchronous Mode
In the normal asynchronous mode, the receive shift register receives the incoming data on
the RXD pin. The length and the format of the serial word in bits are defined by the control
bits in the UART mode register. The order of reception is as follows:
The receiver samples each bit of the incoming data three times around its center. The value
of the bit is determined by the majority of those samples. If all the samples do not agree, a
noise indication counter is incremented. When a complete character has been clocked in,
the contents of the shift register are transferred to the UART receive data register. If there
is an error in this character, then the appropriate error bits will be set by the IMP.
MOTOROLA
• Flexible Message-Oriented Data Buffers
• Multidrop Operation
• Receiver Wakeup on IDLE Line or Address Mode
• Eight Control Character Comparison Registers
• Two Address Comparison Registers
• Four 16-Bit Error Counters
• Programmable Data Length (7 or 8 Bits)
• Programmable 1 or 2 Stop Bits with Fractional Stop Bits
• Even/Odd/Force/No Parity Generation
• Even/Odd/No Parity Check
• Frame Error, Noise Error, Break, and IDLE Detection
• Transmits Preamble and Break Sequences
• Freeze Transmission Option
• Maintenance of Four 16-Bit Error Counters
• Provides Asynchronous Link for DDCMP Use
• Flow Control Character Transmission Supported
Start Bit
Seven or Eight Data Bits with the Least Significant Bit First
Address/Data Bit (Optional)
Parity Bit (Optional)
Stop Bits
MC68302 USER’S MANUAL
Communications Processor (CP)
4-45
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