MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 390
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
MC68302 Applications
In the application described, RESET is driven from a parallel output pin, PA8, of the
MC68302.
D.6.14 Initialization of the MC145475
The following tables show the initialization sequence after power-on reset (assuming the
registers have default values).
If configured as NT, a possible initialization sequence is as follows:
If configured as TE, a possible initialization sequence is as follows:
D-40
Byte Register #7 (BR7)
Nibble Register #4 (NR4)
Byte Register #7 (BR7)
Nibble Register #4 (NR4)
Nibble Register #5 (NR5)
BR5) to their default value. RESET should be asserted after power-on and negated for
normal operation.
Register
Register
MC68302
In the application described, power-on reset to the S/T chip is
provided from one of the parallel output pins (PA8). It is the re-
sponsibility of software to reset the S/T chip after power-up.
Nibble register 2 allows activation (TE/NT) and deactivation (NT)
of the S/T loop. To activate the loop, write $8 to NR2. To deacti-
vate the loop, write $4 to NR2.
Figure D-17. Discrete Signal Interconnection
IRQ1
PA8
MC68302 USER’S MANUAL
Value (hex)
Value (hex)
$0C
$04
$C
—
—
NOTE
IDL master mode; 2-MHz IDL clock (suitable for
the MC145554 CODEC).
Interrupt mask—according to the application.
2-MHz IDL clock (suitable for the MC145554
CODEC).
Interrupt mask—according to the application.
Enables B1 and B2 on S/T loop (with accor-
dance to signaling on the D-channel).
IRQ
RESET
Comments
Comments
MC145475
MOTOROLA
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