MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 198

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
CR—Rx CRC Error
OV—Overrun
CD—Carrier Detect Lost
Data Length
Rx Buffer Pointer
4.5.12.11 HDLC Transmit Buffer Descriptor (Tx BD)
Data is presented to the HDLC controller for transmission on an SCC channel by arranging
it in buffers referenced by the channel's Tx BD table. The HDLC controller confirms trans-
mission (or indicates error conditions) using the BDs to inform the M68000 core that the buff-
ers have been serviced. The Tx BD is shown in Figure 4-28.
4-78
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
This frame contains a CRC error.
A receiver overrun occurred during frame reception.
The carrier detect signal was negated during frame reception. This bit is valid only when
working in NMSI mode.
The data length is the number of octets written to this BD's data buffer by the HDLC con-
troller. It is written by the CP once as the BD is closed.
When this BD is the last BD in the frame (L = 1), the data length contains the total number
of frame octets (including any previous linked receive data buffers and two or four bytes
for the CRC) in the frame. This behavior is useful for determining the total number of oc-
tets received, even if MFLR was exceeded.
The receive buffer pointer, which always points to the first location of the associated data
buffer, may reside in either internal or external memory.
15
R
The actual amount of memory allocated for this buffer should be
even and greater than or equal to the contents of maximum re-
ceive buffer length register (MRBLR).
The Rx buffer pointer must be even, and the upper 8 bits must
of the pointer must be zero for the function codes to operate cor-
rectly.
14
X
Figure 4-28. HDLC Transmit Buffer Descriptor
13
W
DATA LENGTHTX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
12
I
11
L
MC68302 USER’S MANUAL
TC
10
—
NOTE
NOTE
9
—
8
—
7
—
6
—
5
—
4
—
3
—
2
MOTOROLA
UN
1
CT
0