MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 125

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

The SDMA will assert the external BCLR pin when it requests the bus. BCLR can be used
to clear an external bus master from the external bus, if desired. For instance, BCLR can be
connected through logic to the external master's HALT signal, and then be negated exter-
nally when the external master's AS signal is negated. BCLR as seen from the MC68302 is
negated by the SDMA during its access to memory.
The SDMA keeps the M68000 bus for only one operand (8 or 16 bit) transfer before giving
it up. If the SDMA begins a word operation on an 8-bit bus, it will complete that operation
before giving up the bus, unless a bus exception such as reset, halt, retry, or bus error oc-
curs. Reset suspends and resets all SDMA activity. Halt suspends activity after the current
bus cycle. For information on a bus error during an SDMA access, see 4.5.8.4 Bus Error on
SDMA Access.
SDMA operation occurs regardless of the value of the BCLM bit in the SCR, and thus is not
affected by the low interrupt latency mechanism.
4.3 COMMAND SET
The M68000 core processor (or an external processor) issues commands to the CP by writ-
ing to the CP command register (CR). Only one CR exists on the MC68302. The M68000
core should set the least significant bit (FLG) of the command register when it issues com-
mands. The CP clears FLG after completing the command to indicate to the M68000 core
that it is ready for the next command. Subsequent commands to the CR may be given only
after FLG is cleared. The software reset (issued with the RST bit) command may be given
regardless of the state of FLG, but the M68000 core should still set FLG when setting RST.
The CR, an 8-bit, memory-mapped, read-write register, is cleared by reset.
RST—Software Reset Command
GCI-OPCODE—GCI Commands and Command Opcodes
MOTOROLA
This bit is set by the M68000 core and cleared by the CP. This command is useful when
the M68000 core wants to reset the registers and parameters for all channels (SCCs,
SCP, SMCs). The main controller in the CP detects this command by hardware, clears
the FLG bit within two clocks, and resets the entire CP in approximately 60 clocks. User
initialization of the CP registers may begin as soon as the FLG bit is cleared. The CP reset
resets the SCCs to the state following a hardware reset, but it does not affect the serial
interface (the port A and B registers, the configuration of the SIMODE and SIMASK reg-
isters, and the SCON registers). Note that this operation does not clear IPR bits in the in-
terrupt controller.
0 = When the GCI bit is zero, the commands are as follows:
RST
7
GCI
6
MC68302 USER’S MANUAL
5
OPCODE
4
—
3
2
CH. NUM.
Communications Processor (CP)
1
FLG
0
4-5