MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 9

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.5.12.1
4.5.12.2
4.5.12.3
4.5.12.4
4.5.12.5
4.5.12.6
4.5.12.7
4.5.12.8
4.5.12.9
4.5.12.10
4.5.12.11
4.5.12.12
4.5.12.13
4.5.13
4.5.13.1
4.5.13.2
4.5.13.3
4.5.13.4
4.5.13.5
4.5.13.6
4.5.13.7
4.5.13.8
4.5.13.9
4.5.13.10
4.5.13.11
4.5.13.12
4.5.13.13
4.5.13.14
4.5.14
4.5.14.1
4.5.14.2
4.5.14.3
4.5.14.4
4.5.14.5
4.5.14.6
4.5.14.7
4.5.14.8
4.5.14.9
4.5.14.10
4.5.14.11
4.5.14.12
4.5.14.13
4.5.15
4.5.15.1
Paragraph
Number
MOTOROLA
HDLC Channel Frame Transmission Processing.................................. 4-68
HDLC Channel Frame Reception Processing....................................... 4-68
HDLC Memory Map............................................................................... 4-69
HDLC Programming Model ................................................................... 4-69
HDLC Command Set............................................................................. 4-70
HDLC Address Recognition .................................................................. 4-71
HDLC Maximum Frame Length Register (MFLR) ................................. 4-71
HDLC Error-Handling Procedure........................................................... 4-72
HDLC Mode Register ............................................................................ 4-73
HDLC Receive Buffer Descriptor (Rx BD)............................................. 4-75
HDLC Transmit Buffer Descriptor (Tx BD) ............................................ 4-78
HDLC Event Register ............................................................................ 4-80
HDLC Mask Register............................................................................. 4-82
BISYNC Controller ................................................................................ 4-82
Bisync Channel frame Transmission Processing .................................. 4-84
Bisync Channel Frame Reception Processing ...................................... 4-85
Bisync Memory Map.............................................................................. 4-85
BISYNC Command Set ......................................................................... 4-86
BISYNC Control Character Recognition................................................ 4-87
BSYNC-BISYNC SYNC Register .......................................................... 4-89
BDLE-BISYNC DLE Register ................................................................ 4-89
BISYNC Error-Handling Procedure ....................................................... 4-90
BISYNC Mode Register......................................................................... 4-91
BISYNC Receive Buffer Descriptor (Rx BD) ......................................... 4-93
BISYNC Transmit Buffer Descriptor (Tx BD)......................................... 4-95
BISYNC Event Register ........................................................................ 4-97
BISYNC Mask Register ......................................................................... 4-98
Programming the BISYNC Controllers .................................................. 4-99
DDCMP Controller............................................................................... 4-100
DDCMP Channel Frame Transmission Processing ............................ 4-101
DDCMP Channel Frame Reception Processing. ................................ 4-102
DDCMP Memory Map ......................................................................... 4-103
DDCMP Programming Model.............................................................. 4-104
DDCMP Command Set. ...................................................................... 4-104
DDCMP Control Character Recognition.............................................. 4-105
DDCMP Address Recognition. ............................................................ 4-106
DDCMP Error-Handling Procedure ..................................................... 4-106
DDCMP Mode Register....................................................................... 4-108
DDCMP Receive Buffer Descriptor (Rx BD) ....................................... 4-109
DDCMP Transmit Buffer Descriptor (Tx BD)....................................... 4-112
DDCMP Event Register....................................................................... 4-114
DDCMP Mask Register ....................................................................... 4-115
V.110 Controller .................................................................................. 4-115
Bit Rate Adaption of Synchronous Data Signaling Rates
up to 19.2 kbps.................................................................................... 4-116
MC68302 USER’S MANUAL
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Table of Contents
Number
Page
ix