MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 58

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

System Integration Block (SIB)
DNS—Done Not Synchronized
BES—Bus Error Source
BED—Bus Error Destination
DONE—Normal Channel Transfer Done
3.1.3 Interface Signals
The IDMA channel has three dedicated control signals: DMA request (DREQ), DMA ac-
knowledge (DACK), and end of IDMA transfer (DONE). The IDMA’s use of the bus arbitra-
tion signals is described in 3.1.6 DMA Bus Arbitration. The peripheral used with these
signals may be either a source or a destination of the transfers.
3.1.3.1 DREQ and DACK
These are handshake signals between the peripheral requiring service and the IMP. When
the peripheral requires IDMA service, it asserts DREQ, and the IMP begins the IDMA pro-
cess. When the IDMA service is in progress, DACK is asserted during accesses to the de-
vice. These signals are not used when the IDMA is programmed to internal request modes.
3.1.3.2 DONE
This bidirectional signal is used to indicate the last IDMA transfer. With internal request
modes, the IDMA activates DONE as an output during the last IDMA bus cycle. If DONE is
externally asserted during internal request modes, the IDMA transfer is terminated. With ex-
ternal request modes, DONE may be used as an input to the IDMA controller indicating that
the device being serviced requires no more transfers and that the transmission is to be ter-
minated. DONE is an output if the transfer count is exhausted.
3-8
This bit is set if operand packing is performed between 16-bit memory and an 8-bit periph-
eral and the DONE signal is asserted as an input to the IDMA (i.e., by the peripheral) dur-
ing the first access of the 8-bit peripheral. In such a case, the IDMA will still attempt to
finish the second access of the 8-bit peripheral even though DONE has been asserted
(the access could be blocked with external logic); however, the DNS bit will be set to sig-
nify this condition. DNS will not be set if the transfer is terminated by an odd byte count,
since, in this case, the exact number of requested bytes will be transferred by the IDMA.
This bit indicates that the IDMA channel terminated with an error returned during the read
cycle. The channel terminates the IDMA operation without setting DONE. BES is cleared
by writing a one or by setting RST in the CMR. Writing a zero has no effect on BES.
This bit indicates that the IDMA channel terminated with an error during the write cycle.
The channel terminates the IDMA operation without setting DONE. BED is cleared by writ-
ing a one or by setting RST in the CMR. Writing a zero has no effect on BED.
This bit indicates that the IDMA channel has terminated normally. Normal channel termi-
nation is defined as 1) having decremented the BCR to zero with no errors occurring dur-
ing any IDMA transfer bus cycle or 2) by the external peripheral asserting DONE with no
errors occurring during any IDMA transfer bus cycle. DONE will not be set if the channel
terminates due to an error. DONE is cleared by writing a one or by a software RST in the
CMR. Writing a zero has no effect on this bit.
MC68302 USER’S MANUAL
MOTOROLA